Multilayers of nickel alloys as diffusion barrier layers

ABSTRACT

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1&lt;a2. The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a division of U.S. patent application Ser. No.16/909,649, filed Jun. 23, 2020, which is a continuation of U.S. patentapplication Ser. No. 16/038,598, filed Jul. 18, 2018 now U.S. Pat. No.10,692,830, which claims priority to U.S. Provisional Application No.62/611,432, filed Dec. 28, 2017, and U.S. Provisional Application No.62/568,429, filed Oct. 5, 2017, which are hereby incorporated byreference.

BACKGROUND

Wafer bumping is a requirement for board level semiconductor packagingwhereby bumps or balls made of solder are formed on the wafers in awhole wafer prior to dicing of wafer into individual chips. Theelectromigration failure mode of bumps resulting from interdiffusion ofcopper (Cu) and tin (Sn) is a significant problem in semiconductordevices.

SUMMARY

In order to solve the above problem, it is desirable to provide asemiconductor device formed by electrodeposition of multilayers ofnickel (Ni) alloys on Cu that is able to overcome the abovedisadvantage. Advantages of the present invention will become more fullyapparent from the detailed description of the invention hereinbelow.

In one aspect of the disclosure, a structure for a semiconductor deviceincludes a Cu layer and a first Ni alloy layer with a Ni grain size a₁.The structure also includes a second Ni alloy layer with a Ni grain sizea₂, wherein a₁<a₂. The first Ni alloy layer is between the Cu layer andthe second Ni alloy layer. The structure further includes a Sn layer ora Sn alloy such as Sn—Ag, Sn—Cu—Ag, Sn—Bi, etc. The second Ni alloylayer is between the first Ni alloy layer and the Sn layer.

In another aspect of the disclosure, an integrated circuit (IC) packageincludes a die and a bump electrically connected to the die. The bumpincludes a Cu layer and a first nickel tungsten (NiW) layer, with a Nigrain size a₁, formed over the Cu layer. The bump also includes a secondNiW layer, with a Ni grain size a₂, formed over the first NiW layer. Thebump further includes a third NiW layer, with a Ni grain size a₃, formedover the second NiW layer, wherein a₁<a₂<a₃. A Sn layer is formed overthe third NiW layer.

In yet another aspect of the disclosure, a method of forming anintegrated circuit package includes forming a die and forming a bump onthe die such that the bump is electrically connected to the die. Theforming of the bump includes forming a first Ni alloy layer, with a Nigrain size a₁, over a Cu layer. The forming of the bump also includesforming a second Ni alloy layer, with a Ni grain size a₂, over the firstNi alloy layer, wherein a₁<a₂. The forming of the bump further includesforming a Sn layer over the second Ni alloy layer.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of various examples, reference will now bemade to the accompanying drawings in which:

FIG. 1 is a side view of an IC package;

FIG. 2 is a side view of a multilayered structure of a bump, inaccordance with this disclosure;

FIG. 3 is a side view of another multilayered structure of a bump, inaccordance with this disclosure;

FIG. 4 is a side view of yet another multilayered structure of a bump,in accordance with this disclosure;

FIG. 5 is a side view of an IC package including a multilayered bumpstructure, in accordance with this disclosure;

FIG. 6 is a plot depicting an example of a reversed pulse waveform thatmay be applied to form Ni alloy layers of a structure for asemiconductor device, in accordance with this disclosure;

FIG. 7 is a flowchart illustrating an exemplary method for forming anintegrated circuit package, in accordance with this disclosure;

FIG. 8 is a side view of yet another multilayered structure of a bump,in accordance with this disclosure; and

FIG. 9 is a flowchart illustrating an exemplary method for forminganother integrated circuit package, in accordance with this disclosure.

DETAILED DESCRIPTION

Certain terms have been used throughout this description and claims torefer to particular system components. As one skilled in the art willappreciate, different parties may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In this disclosure and claims, theterms “including” and “comprising” are used in an open-ended fashion,and thus should be interpreted to mean “including, but not limited to. .. . ” Also, the term “couple” or “couples” is intended to mean either anindirect or direct wired or wireless connection. Thus, if a first devicecouples to a second device, that connection may be through a directconnection or through an indirect connection via other devices andconnections. The recitation “based on” is intended to mean “based atleast in part on.” Therefore, if X is based on Y, X may be a function ofY and any number of other factors.

The increasing demand for miniaturization of semiconductor packages (orIC packages) necessitates the increased current density (amount ofcurrent per surface area) per bump. FIG. 1 displays a schematic diagramof an IC package with the bumps. Therefore, the electromigration failuremode of bumps is critical to determine the bump current carryingcapability. Electromigration is the transport of material as a result ofgradual movement of the ions in a conductor due to the momentum transferbetween conducting electrons and diffusing metal atoms. Electromigrationdegrades the reliability of chips resulting in eventual loss ofconnections or failure of a circuit. The electromigration effect becomesmore important with the reduction in the structure size in electronicssuch as ICs. Electromigration failure in Cu pillar bumps and also insolder bumps is attributed to the depletion of intermetallic compoundsat the interface of Cu and Sn.

Both the growth of intermetallic compounds (IMCs) between Cu and Sn andvoid formation affect the solder joint reliability, which can degradethe mechanical and electrical properties of the joints. The mechanism ofvoid formation in the Cu/Sn system is basically caused by unbalanceddiffusion rates of Cu and Sn in which the diffusion rate of copper ishigher than that of tin in the Cu₃Sn phase (the Kirkendall effect). TheKirkendall effect is the motion of the interface between two metals thatoccurs as a result of the difference in diffusion rates of the metalatoms. The Kirkendall effect has important practical consequences. Oneof these is the prevention or suppression of voids formed at theboundary interface in various kinds of alloy-to-metal bonding. These arereferred to as Kirkendall voids.

Voiding and micro-cracks elimination and/or reduction at the Cu—Sninterface can be achieved through insertion of multilayered (ormultilayers of) NiW with controlled grain size. The Cu—Sn intermetalliclayer is dominated by formation of Cu₆Sn₅ (η) phase and a limited amountof Cu₃Sn (ε) is formed as a non-continuous layer at the Cu surface. Ingeneral, the η-phase shows extensive scalloping with a pattern similarto the ε-islands. The Kirkendall voids are usually present in theCu₃Sn-phase mainly in the adjacent of the Cu—Cu₃Sn interface and on theinterface itself and the Cu₃Sn layer grows at the expense of Cu₆Sn₅ aslong as there is a sufficient source of Cu. Therefore, insertion of anintermediate diffusion barrier layer at the Cu—Sn interface can decreaseand/or eliminate the inter-diffusion of Cu and Sn. When Ni alone hasbeen used as a diffusion barrier layer, formation of brittleintermetallic compounds of Ni₃Sn₄ at the Sn and Ni interface occurswhich imposes reliability issues. The presence of dissolved Cu into theNi₃Sn₄ slows down the intermetallic growth. However, the amount of theCu needs to be small enough to form (Cu,Ni)3Sn4. Presence of too much Curesults in formation of a Cu/Ni-intermetallic with theCu₆Sn₅-stoichiometry resulting in extensive scalloping.

Pulsed Electrodeposition of multiple NiW layers with Controlled GrainStructure as a Diffusion Barrier Layer is the solution to theseproblems. Interfacing of NiW at the Cu and Sn interface through reversedpulse electrodeposition in which the Ni grain size of theelectrodeposited NiW may be precisely controlled by using a particularplating chemistry together with a reversed pulse waveform is disclosed.Using this reversed pulse plating, anodic and cathodic pulses orwaveforms are mixed where cathodic pulses are followed by anodic pulses.

Application of multiple layers of NiW through electrodeposition in whichthe first layer 301 (see FIG. 4) has a grain size of a₁, a second layer402 has a grain size of a₂, and, if employed, a third layer 403 has agrain size of a₃, where a₁<a₂<a₃. Some amount of the codeposited W issolubilized in crystal structure of Ni grain and the rest is segregatedat the grain boundary of Ni. The content (% by weight) of thecodeposited W (i.e., with respect to the entire NiW layer) is inverselyrelated to the size of the grains. Therefore, through precisecontrolling of codeposited W, it is possible to control the grain sizeof Ni precisely. The amount of codeposited tungsten (W) depends on thetype of the applied reversed pulse waveform; meaning that the cathodicand anodic current densities as well as their pulse duration influencethe amount of codeposited tungsten. The content of codeposited tungsteninfluences the size of nickel (Ni) grains. Therefore, by precisecontrolling of the anodic and cathodic current densities and their pulseduration, it is possible to precisely control the grain size of nickel(Ni). The segregation of W at the grain boundary of Ni blocks thediffusion of the Cu through the grain boundary path. Also, Ni within thehigher layer (as oriented in FIG. 4) having larger grain size would havea tendency to diffuse towards the layer with smaller grain size.Therefore, the Ni in the layer 403 will have tendency to diffuse towardslayer 402 and the Ni in layer 402 would have a tendency to diffusetowards layer 401. This is expected to slow down or eliminate the Nidiffusion from layer 403 to the Sn layer due to its tendency fordiffusion towards its under layer. On the other hand, it is expectedthat the segregated W at the Ni grain boundary would slow down oreliminate the formation of a brittle Ni₃Sn₄ intermetallic compound.

Insertion of multilayered NiW at the Cu—Sn interface solves the aboveproblems. A multilayered deposition process is performed in which theNiW layers are deposited with gradually increasing Ni grain sizestarting from the Cu layer. This results in, inter alia, segregation ofW at grain boundaries of Ni, thereby improving electromigrationperformance.

Reversed pulse electrodeposition slows down or eliminates the formationof a brittle Ni₃Sn₄ intermetallic layer that would otherwise be formedat the interface of Sn and Ni.

The segregation of W in the Ni grain boundary slows down or eliminatesthe diffusion of Cu through grain boundary paths resulting in a moreefficient diffusion barrier compared to Ni alone.

The deposition of multilayered NiW with precise control of grain sizeallows enforcement of the direction of Ni diffusion to be towards theunderlayer NiW layer having smaller grain size (i.e., in a directiontoward the Cu layer). This results in slowing down or elimination of Nidiffusion towards the Sn layer, hence reducing the thickness of anypossible-formed Ni₃Sn₄ intermetallic compound which is brittle innature. On the other hand, the solid solubility of Ni in Cu wouldprovide good adhesion at the first NiW layer 401 and the Cu layer 410interface (FIG. 4).

Reversed pulse electrodeposition allows for adjustment of the Ni grainsize hence enforcing the Ni diffusion more towards the underlayer NiWlayer as compared to toward the Sn layer.

Reversed pulse electrodeposition allows precise control of the graingrowth of Ni and the precise amount of segregated W. Reversed pulseelectrodeposition also allows for electrodeposition of multiple layersof NiW with gradually increasing grain size of nickel during the platingresulting in enforcement of Ni diffusion towards its underlayer of NiW(e.g., towards the lower Ni alloy layers in FIGS. 2 and 3, or the lowerNiW layers in FIG. 4) that has smaller Ni grain size.

FIGS. 2-4 show, inter alia, a particular grain size arrangement within amultilayered structure of a bump.

With reference to FIG. 2, in one aspect of the disclosure, a structure200 for a semiconductor device includes a Cu layer 210 and a first Nialloy layer 201 with a Ni grain size a₁. The structure 200 also includesa second Ni alloy layer 202 with a Ni grain size a₂, wherein a₁<a₂. Thefirst Ni alloy layer 201 is between the Cu layer 210 and the second Nialloy layer 202. The structure 200 further includes a Sn layer 220. Snlayer 220 may optionally be comprised of a Sn alloy such as Sn—Ag,Sn—Cu—Ag, Sn—Bi, etc. The second Ni alloy layer 202 is between the firstNi alloy layer 201 and the Sn layer 220.

In an example, the first Ni alloy layer 201 and the second Ni alloylayer 202 each comprises at least one element selected from the groupconsisting of tungsten (W), molybdenum (Mo), an element from alanthanoid group, and combinations thereof.

In an example, a % by weight (x₁) of the at least one element within thefirst Ni alloy layer 201 is present, a % by weight (x₂) of the at leastone element within the second Ni alloy layer 202 is present, and whereinx₁>x₂.

In an example, the first Ni alloy layer 201 may be formed over the Culayer 210, and the Sn layer 220 may be formed over the second Ni alloylayer 202.

In an example, some of the at least one element in the first Ni alloylayer 201 and some of the at least one element in the second Ni alloylayer 202 are solubilized in the Ni grains, while a remainder of the atleast one element in the first Ni alloy layer 201 and a remainder of theat least one element in the second Ni alloy layer 202 are segregated atboundaries of the Ni grains.

In an example, the first Ni alloy layer 201 comprises NiW.

In an example, the second Ni alloy layer 202 comprises NiW.

In an example, the first Ni alloy layer 201 comprises NiCe, NiLa, NiMo,NiMoW, or NiWCe.

In an example, the second Ni alloy layer 202 comprises NiCe, NiLa, NiMo,NiMoW, or NiWCe.

With reference to FIG. 3, in another aspect of the disclosure, astructure 300 for a semiconductor device includes a Cu layer 310 and afirst Ni alloy layer 301 with a Ni grain size a₁. The structure 300 alsoincludes a second Ni alloy layer 302 with a Ni grain size a₂, whereina₁<a₂. The first Ni alloy layer 301 is between the Cu layer 310 and thesecond Ni alloy layer 302. The structure 300 further includes a third Nialloy layer 303 with a Ni grain size a₃, formed over the second Ni alloylayer 302, and a Sn layer 320 is formed over the third Ni alloy layer303, wherein a₁<a₂<a₃.

In an example, the first Ni alloy layer 301, the second Ni alloy layer302, and the third Ni alloy layer 303 each comprises at least oneelement selected from the group consisting of tungsten (W), molybdenum(Mo), an element from a lanthanoid group, and combinations thereof. A %by weight (x₁) of the at least one element within the first Ni alloylayer 301 is present, a % by weight (x₂) of the at least one elementwithin the second Ni alloy layer 302 is present, a % by weight (x₃) ofthe at least one element within the third Ni alloy layer 303 is present,and wherein x₁>x₂>x₃.

With reference to FIG. 4, in another aspect of the disclosure, astructure 400 for a semiconductor device includes a Cu layer 410 and afirst nickel tungsten (NiW) layer 401, with a Ni grain size a₁, formedover the Cu layer 410. The structure 400 also includes a second NiWlayer 402, with a Ni grain size a₂, formed over the first NiW layer 401.The structure 400 further includes a third NiW layer 403, with a Nigrain size a₃, formed over the second NiW layer 402, wherein a₁<a₂<a₃. ASn layer 420 is formed over the third NiW layer 403.

With reference to FIG. 5, in another aspect of the disclosure, an ICpackage/die includes a multilayered bump (also shown in FIG. 4). Withspecific reference back to FIG. 4, the multilayered bump 400 includes aCu layer 410 and a first nickel tungsten (NiW) layer 401, with a Nigrain size a₁, formed over the Cu layer 410. The bump 400 also includesa second NiW layer 402, with a Ni grain size a₂, formed over the firstNiW layer 401. The bump 400 further includes a third NiW layer 403, witha Ni grain size a₃, formed over the second NiW layer 402, whereina₁<a₂<a₃. A Sn layer 420 is formed over the third NiW layer 403.

In an example, a % by weight (x₁) of the W within the first NiW layer401 is present, a % by weight (x₂) of the W within the second NiW layer402 is present, and a % by weight (x₃) of the W within the third NiWlayer 403 is present, and wherein x₁>x₂>x₃.

In an example, the first NiW layer 401 and/or the second NiW layer 402comprise an element from a lanthanoid group.

In an example, some W in the first NiW layer 401, second NiW layer 402,and third NiW layer 403 is solubilized in the Ni grains, while theremainder of the W in the first NiW layer 401, second NiW layer 402, andthird NiW layer 403 is segregated at boundaries of the Ni grains.

With reference to FIG. 7, In yet another aspect of the disclosure, amethod 700 of forming an integrated circuit package includes forming adie (block 702) and forming a bump on the die such that the bump iselectrically connected to the die (block 704). The forming of the bumpincludes forming a first Ni alloy layer, with a Ni grain size a₁, over aCu layer. The forming of the bump also includes forming a second Nialloy layer, with a Ni grain size a₂, over the first Ni alloy layer,wherein a₁<a₂. The forming of the bump further includes forming a Snlayer over the second Ni alloy layer.

In an example of the method, the first Ni alloy layer and the second Nialloy layer each comprises at least one element selected from the groupconsisting of tungsten (W), molybdenum (Mo), an element from alanthanoid group, and combinations thereof.

In an example of the method, a % by weight (x₁) of the at least oneelement within the first Ni alloy layer is present, a % by weight (x₂)of the at least one element within the second Ni alloy layer is present,and wherein x₁>x₂.

In an example of the method, the forming of the first Ni alloy layer andthe second Ni alloy layer are performed via a reversed pulseelectrodeposition process.

In an optional process step (and with reference to FIGS. 8 and 9), oncethe multiple Ni alloy layers are formed, and before the Sn layer isformed thereon, the structure may be heated to a temperature betweenabout 100-200° C. for a period of about 4-5 hours. This optional processstep would melt or fuse the multiple Ni alloy layers together, therebyforming a single Ni alloy layer. This single Ni alloy layer, as a whole,would effectively have substantially similar properties (e.g., thelocation and distribution of the Ni grain sizes and W content % byweight) as those of the multiple Ni alloy layers. The resultantstructure is shown in FIG. 8.

With reference to FIG. 8, in another aspect of the disclosure, astructure 800 for a semiconductor device includes a Cu layer 810 and aNi alloy layer 801 with Ni grain sizes a₁and a₂, wherein a₁<a₂. Thestructure 800 further includes a Sn layer 820. Sn layer 820 mayoptionally be comprised of a Sn alloy such as Sn—Ag, Sn—Cu—Ag, Sn—Bi,etc. The Ni alloy layer 801 is between the Cu layer 810 and the Sn layer820.

In an example, the Ni grains of size a₁ within the Ni alloy layer issubstantially closer to the Cu layer than the Sn layer, and the Nigrains of size a₂ within the Ni alloy layer is substantially closer tothe Sn layer than the Cu layer.

In an example, the Ni grain size a₁ is between 1 nm and 100 nm indiameter, and the Ni grain size a₂ is between 2 nm and 100 nm indiameter.

In an example, the Ni alloy layer comprises at least one elementselected from the group consisting of tungsten (W), molybdenum (Mo), anelement from a lanthanoid group, and combinations thereof.

In an example, a % by weight (x₁) of the at least one element within theNi alloy layer is present, a % by weight (x₂) of the at least oneelement within the Ni alloy layer is present, and wherein x₁>x₂.

In an example, the at least one element at x₁ within the Ni alloy layeris substantially closer to the Sn layer than the Cu layer, and the atleast one element at x₂ within the Ni alloy layer is substantiallycloser to the Cu layer than the Sn layer.

In an example, some of the at least one element at x₁ within the Nialloy layer and some of the at least one element at x₂ within the Nialloy layer are solubilized in the Ni grains, while a remainder of theat least one element at x₁ within the Ni alloy layer and a remainder ofthe at least one element at x₂ within the Ni alloy layer are segregatedat boundaries of the Ni grains.

In an example, the Ni alloy layer comprises NiW.

In an example, the Ni alloy layer comprises NiCe, NiLa, NiMo, NiMoW, orNiWCe.

With reference to FIG. 9, In yet another aspect of the disclosure, amethod 900 of forming an integrated circuit package includes forming adie (block 902) and forming a bump on the die such that the bump iselectrically connected to the die (block 904). The forming of the bumpincludes forming a copper (Cu) layer. The forming of the bump alsoincludes forming a nickel (Ni) alloy layer with Ni grain sizes a₁and a₂,wherein a₁<a₂. The forming of the bump further includes forming a tin(Sn) layer, wherein the Ni alloy layer is between the Cu layer and theSn layer.

In an example of the method, the Ni grains of size a₁ within the Nialloy layer is substantially closer to the Cu layer than the Sn layer,and the Ni grains of size a₂within the Ni alloy layer is substantiallycloser to the Sn layer than the Cu layer.

In an example of the method, the Ni alloy layer comprises at least oneelement selected from the group consisting of tungsten (W), molybdenum(Mo), an element from a lanthanoid group, and combinations thereof.

In an example of the method, a % by weight (x₁) of the at least oneelement within the Ni alloy layer is present, a % by weight (x₂) of theat least one element within the Ni alloy layer is present, and whereinx₁>x₂.

In an example of the method, the at least one element at x₁ within theNi alloy layer is substantially closer to the Sn layer than the Culayer, and the at least one element at x₂ within the Ni alloy layer issubstantially closer to the Cu layer than the Sn layer.

In an example of the method, the forming of the Ni alloy layer comprisesheating and melting together of multiple pre-heated Ni alloy layers,prior to the forming of the Sn layer.

Reversed Pulse Plating

Examples below describe reverse pulse electrodeposition processesincluding, inter alia, current density and pulse durationcharacteristics. In pulse reverse plating (PRP), the potential voltageand/or current is alternated between cathodic and anodic pulses.Cathodic and anodic pulses are characterized by their amplitude (peakvoltage and/or peak current density) and pulse duration. Each pulse mayconsist of an OFF time (T_(OFF)) during which the applied current iszero. FIG. 6 is a plot 600 depicting an example of a reversed pulsewaveform that may be applied to form Ni alloy layers between Cu and Snlayers in any of the aspects of the disclosure. The combination of theCu and Sn layers and the intermediary Ni alloy layers form a structurefor a semiconductor device. As it can be seen in FIG. 6, each cathodicpulse consists of an ON-time pulse duration (T_(ON,cathodic)) duringwhich negative potential and/or negative current is applied, and anOFF-time (T_(OFF,cathodic)) during which zero current is applied. Eachanodic pulse consists of an ON-time pulse duration (T_(ON,anodic))during which positive potential and/or positive current is applied, andan OFF-time (T_(OFF,anodic)) during which zero current is applied.

The deposited film composition (e.g., the content (% by weight) ofco-deposited W in electrodeposition of NiW alloys) may be controlled inan atomic order by regulating the pulse amplitude and width, whichfosters the initiation of grain nuclei and greatly increases the numberof grains per unit area resulting in finer-grained deposit with betterproperties as compared to direct current (DC) plated coatings.

High current density areas in the bath (i.e., plating solution) becomemore depleted of ions than low current density areas. During T_(OFF),ions migrate to the depleted areas in the bath. Therefore, during theT_(ON), more evenly distributed ions would be available forelectrodeposition.

Table 1 and Table 2 below show an example of the waveform than can beused for depositing of first and second layers of NiW, respectively. Theaverage current density (I_(Average)) is calculated using Equation 1.

I _(Average)=(I_(Cathodic,ON) ×T _(Cathodic,ON) −I _(anodic,ON) ×T_(Anodic,ON))/(T _(Cathodic,ON) +T _(Cathodic,OFF) +T _(Anodic,ON) +T_(Anodic,OFF))  (Equation 1)

TABLE 1 Pulse waveform characteristics for depositing of the first layerof NiW. Pulse characterization Symbol Value Cathodic pulse amplitude(current density) I_(Cathodic, ON)  0.5 A/cm² Cathodic pulse durationduring ON time T_(Cathodic, ON)   20 ms Cathodic OFF timet_(Cathodic, OFF)    0 Anodic pulse amplitude (current density)I_(Anodic, ON)  0.3 A/cm² Anodic pulse duration during ON timeT_(Anodic, ON)   13 ms Anodic OFF time T_(Anodic, OFF)    0 Averagecurrent density I_(Average) 0.185 A/cm²

TABLE 2 Pulse waveform characteristics for depositing of the secondlayer of NiW. Pulse characterization Symbol Value Cathodic pulseamplitude (current density) I_(Cathodic, ON)  0.5 A/cm² Cathodic pulseduration during ON time T_(Cathodic, ON)   20 ms Cathodic OFF timet_(Cathodic, OFF)    0 Anodic pulse amplitude (current density)I_(Anodic, ON)  0.4 A/cm² Anodic pulse duration during ON timeT_(Anodic, ON)   15 ms Anodic OFF time T_(Anodic, OFF)    0 Averagecurrent density I_(Average) 0.114 A/cm²

Table 3 and Table 4 below show another example of the waveform than canbe used for depositing of first and second layers of NiW, respectively.The average current density (I_(Average)) is calculated using Equation1.

TABLE 3 Pulse waveform characteristics for depositing of the first layerof NiW. Pulse characterization Symbol Value Cathodic pulse amplitude(current density) I_(Cathodic, ON)  0.6 A/cm² Cathodic pulse durationduring ON time T_(Cathodic, ON)   20 ms Cathodic OFF timet_(Cathodic, OFF)    1 Anodic pulse amplitude (current density)I_(Anodic, ON)  0.4 A/cm² Anodic pulse duration during ON timeT_(Anodic, ON)   13 ms Anodic OFF time T_(Anodic, OFF)  0.2 Averagecurrent density I_(Average) 0.199 A/cm²

TABLE 4 Pulse waveform characteristics for depositing of the secondlayer of NiW. Pulse characterization Symbol Value Cathodic pulseamplitude (current density) I_(Cathodic, ON)  0.6 A/cm² Cathodic pulseduration during ON time T_(Cathodic, ON)   20 ms Cathodic OFF timet_(Cathodic, OFF)    1 Anodic pulse amplitude (current density)I_(Anodic, ON)  0.5 A/cm² Anodic pulse duration during ON timeT_(Anodic, ON)   13 ms Anodic OFF time T_(Anodic, OFF)  0.5 Averagecurrent density I_(Average) 0.159 A/cm²

Advantages of aspects of the disclosure are, for example, bettercorrosion resistance, better diffusion barrier, precise control of grainsize of deposit, better control of the amount of the segregation ofalloying element (e.g., W), reasonable cost, and/or easy scale-up fromlab scale to production.

Although examples are described above with reference to W as thealloying element within the NiW layers, other alloyingelements/compositions such as Ce, La, Mo, MoW, or WCe may alternativelybe employed in any of the examples above. Such alternatives areconsidered to be within the spirit and scope of the disclosure, and maytherefore utilize the advantages of the configurations and examplesdescribed above.

Also, although examples are described above with reference to structureswith two or three Ni alloy layers, structures with more than three Nialloy layers between the Cu and Sn layers may alternatively be employedin any of the examples above. Such alternatives are considered to bewithin the spirit and scope of the disclosure, and may therefore utilizethe advantages of the configurations and examples described above.

The method steps in any of the embodiments described herein are notrestricted to being performed in any particular order. Also, structuresmentioned in any of the method embodiments may utilize structuresmentioned in any of the device embodiments. Such structures may bedescribed in detail with respect to the device embodiments only but areapplicable to any of the method embodiments.

Features in any of the embodiments described in this disclosure may beemployed in combination with features in other embodiments describedherein, such combinations are considered to be within the spirit andscope of the present invention.

The above discussion is meant to be illustrative of the principles andvarious example implementations according to this disclosure. Numerousvariations and modifications will become apparent to those skilled inthe art once the above disclosure is fully appreciated. It is intendedthat the following claims be interpreted to embrace all such variationsand modifications.

What is claimed is:
 1. A method of forming an integrated circuitpackage, the method comprising: forming a die; and forming a bump on thedie such that the bump is electrically connected to the die, the formingof the bump comprises: forming a first nickel (Ni) alloy layer, with aNi grain size a₁, over a copper (Cu) layer; forming a second Ni alloylayer, with a Ni grain size a₂, over the first Ni alloy layer, whereina₁<a₂; and forming a tin (Sn) layer over the second Ni alloy layer,wherein the alloy in in the first Ni alloy layer and the second Ni alloylayer is co-deposited with Ni, and a percentage weight of the alloy inthe first Ni alloy layer and the second Ni alloy layer is controlled atan atomic order.
 2. The method of claim 1, wherein the first Ni alloylayer and the second Ni alloy layer each comprises at least one elementselected from the group consisting of tungsten (W), molybdenum (Mo), anelement from a lanthanoid group, and combinations thereof.
 3. The methodof claim 2, wherein a % by weight (x₁) of the at least one elementwithin the first Ni alloy layer is present, a % by weight (x₂) of the atleast one element within the second Ni alloy layer is present, andwherein x₁>x₂.
 4. The method of claim 1, wherein the copper layer isover a pad of the die.
 5. The method of claim 1, wherein the firstnickel alloy layer and the second nickel alloy layer include one ofNiCe, NiMoW, and NiWCe.
 6. A method of forming an integrated circuitpackage, the method comprising: forming a die; and forming a bump on thedie such that the bump is electrically connected to the die, the formingof the bump comprises: forming a copper (Cu) layer; forming a nickel(Ni) alloy layer with Ni grain sizes a₁ and a₂, wherein a₁<a₂; andforming a tin (Sn) layer, wherein the Ni alloy layer is between the Culayer and the Sn layer; wherein the alloy in in the Ni alloy layer andthe is co-deposited with Ni, and a percentage weight of the alloy in theNi alloy layer is controlled at an atomic order.
 7. The method of claim6, wherein the Ni grains of size a₁ within the Ni alloy layer issubstantially closer to the Cu layer than the Sn layer, and the Nigrains of size a₂ within the Ni alloy layer is substantially closer tothe Sn layer than the Cu layer.
 8. The method of claim 6, wherein the Nialloy layer comprises at least one element selected from the groupconsisting of tungsten (W), molybdenum (Mo), an element from alanthanoid group, and combinations thereof.
 9. The method of claim 8,wherein a % by weight (x₁) of the at least one element within the Nialloy layer is present, a % by weight (x₂) of the at least one elementwithin the Ni alloy layer is present, and wherein x₁>x₂.
 10. The methodof claim 9, wherein the at least one element at x₁ within the Ni alloylayer is substantially closer to the Sn layer than the Cu layer, and theat least one element at x₂ within the Ni alloy layer is substantiallycloser to the Cu layer than the Sn layer.
 11. A method of forming anintegrated circuit package, the method comprising: forming a die; andforming a bump on the die such that the bump is electrically connectedto the die, the forming of the bump comprises: forming a first nickel(Ni) alloy layer via a reversed pulse electrodeposition process, with aNi grain size a₁, over a copper (Cu) layer; forming a second Ni alloylayer via the reversed pulse electrodeposition process, with a Ni grainsize a₂, over the first Ni alloy layer, wherein a₁<a₂; and forming a tin(Sn) layer over the second Ni alloy layer.
 12. The method of claim 11,wherein the first Ni alloy layer and the second Ni alloy layer eachcomprises at least one element selected from the group consisting oftungsten (W), molybdenum (Mo), an element from a lanthanoid group, andcombinations thereof.
 13. The method of claim 12, wherein a % by weight(x₁) of the at least one element within the first Ni alloy layer ispresent, a % by weight (x₂) of the at least one element within thesecond Ni alloy layer is present, and wherein x₁>x₂.
 14. The method ofclaim 11, wherein the copper layer is over a pad of the die.
 15. Themethod of claim 11, wherein the first nickel alloy layer and the secondnickel alloy layer include one of NiCe, NiMoW, and NiWCe.